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512k x 36/1m x 18 pipelined sram cy7c1380cv25 cy7c1382cv25 preliminary cypress semiconductor corporation ? 3901 north first street san jose, ca 95134 408-943-2600 document #: 38-05240 rev. *a revised november 20, 2002 380cv25 features ? fast clock speed: 250, 225, 200, 167 mhz provide high-performance 3-1-1-1 access rate fast oe access times: 2.6, 2.8, 3.0, 3.4 ns optimal for depth expansion single 2.5v 5% power supply common data inputs and data outputs byte write enable and global write control chip enable for address pipeline address, data, and control registers internally self-timed write cycle burst control pins (interleaved or linear burst sequence) automatic power-down available using zz mode or ce deselect available in 119-ball bump bga, 165-ball fbga and 100-pin tqfp packages jtag boundary scan for bga packaging version functional description the cypress synchronous burst sram family employs high- speed, low-power cmos designs using advanced single-layer polysilicon, triple-layer metal technology. each memory cell consists of six transistors. the cy7c1382cv25 and cy7c1380cv25 srams integrate 1,048,576x18 and 524,288x36 sram cells with advanced synchronous peripheral circuitry and a 2-bit counter for inter- nal burst operation. all synchronous inputs are gated by reg- isters controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce ), burst control in- puts (adsc , adsp , and adv ), write enables (bw a, bw b, bw c, bw d and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and burst mode control (mode). the data (dqa,b,c,d) and the data par- ity (dqpa,b,c,d) outputs, enabled by oe , are also asynchro- nous. dqa,b,c,d and dpa,b,c,d apply to cy7c1380cv25 and dqa,b and dpa,b apply to cy7c1382cv25. a, b, c, d each are of 8 bits wide in the case of dq and 1 bit wide in the case of dp. addresses and chip enables are registered with either address status processor (adsp ) or address status controller (adsc ) input pins. subsequent burst addresses can be internally gen- erated as controlled by the burst advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate self-timed write cycle. write cycles can be one to four bytes wide as controlled by the write control inputs. indi- vidual byte write allows individual byte to be written. bw a con- trols dqa and dpa. bw b controls dqb and dpb. bw c controls dqc and dpd. bw d controls dqd and dpd. bw a, bw b bw c, and bw d can be active only with bwe being low. gw being low causes all bytes to be written. write pass-through capa- bility allows written data available at the output for the next read cycle. this device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. all inputs and outputs of the cy7c1380cv25 and the cy7c1382cv25 are jedec standard jesd8-5 compatible. selection guide 250 mhz 225 mhz 200 mhz 167 mhz unit maximum access time 2.6 2.8 3.0 3.4 ns maximum operating current 350 325 300 275 ma maximum cmos standby current 70 70 70 70 ma shaded areas contain advance information.
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 2 of 33 clk adv adsc a [18:0] gw bwe bw d bw c bw b bw a ce 1 ce 3 ce 2 oe zz burst counter address register output registers input registers 512kx36 memory array clk clk q 0 q 1 q d ce ce clr sleep control 36 36 19 17 17 19 (a [1;0] ) 2 mode adsp dq a,b,c,d dp a,b dqd, dpd bytewrite registers dq dqc, dpc bytewrite registers dq dq dqb, dpb bytewrite registers dqa, dpa bytewrite registers dq enable ce register dq enable delay register dq cy7c1380cv25 - 512k x 36 clk adv adsc a [19:0] gw bwe bw b bw a ce 1 ce 3 ce 2 oe zz burst counter address register output registers input registers memory array clk clk q 0 q 1 q d ce ce clr sleep control 18 18 20 18 18 20 (a [1;0] ) 2 mode adsp cy7c1382cv25 - 1m x 18 dq a,b dp a,b dqb, dpb bytewrite registers dq dqa, dpa bytewrite registers dq enable ce register dq enable delay register dq ce 1m x 18
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 3 of 33 pin configurations a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dpa dqa dqa v ssq v ddq dqa dqa v ss nc v dd zz dqa dqa v ddq v ssq dqa dqa nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dqb dqb v ssq v ddq dqb dqb v dd nc v ss dqb dqb v ddq v ssq dqb dqb dpb nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bwb bwa ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1382cv25 (1m x 18) nc a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a a nc,dqpb dqb dqb v ddq v ssq dqb dqb dqb dqb v ssq v ddq dqb dqb v ss nc v dd zz dqa dqa v ddq v ssq dqa dqa dqa dqa v ssq v ddq dqa dqa nc,dqpa nc,dqpc dqc dqc v ddq v ssq dqc dqc dqc dqc v ssq v ddq dqc dqc v dd nc v ss dqd dqd v ddq v ssq dqd dqd dqd dqd v ssq v ddq dqd dqd nc,dqpd a a ce 1 ce 2 bwd bwc bwb bwa ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1380cv25 (512k x 36) nc a 100-pin tqfp top view
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 4 of 33 119-ball bga pin configurations (continued) 2 3 4 5 6 7 1 a b c d e f g h j k l m n p r t u v ddq nc nc dqpc dqc dqd dqc dqd a a a a adsp v ddq a dqc v ddq dqc v ddq v ddq v ddq dqd dqd nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms 36m 72m nc v ddq v ddq v ddq a a a a a a a a a a a a0 a1 dqa dqc dqa dqa dqa dqb dqb dqb dqb dqb dqb dqb dqa dqa dqa dqa dqb v dd dqc dqc dqc v dd dqd dqd dqd dqd adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss dqpa mode dqpd dqpb bwb bwc nc v dd nc bwa nc bwe bwd zz 2 3 4 5 6 7 1 a b c d e f g h j k l m n p r t u v ddq nc nc nc dqb dqb dqb dqb a a a a adsp v ddq a nc v ddq nc v ddq v ddq v ddq nc nc nc 72m v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms a a nc v ddq v ddq v ddq a 36m a a a a a a a a a a0 a1 dqa dqb nc nc dqa nc dqa dqa nc nc dqa nc dqa nc dqa nc dqa v dd nc dqb nc v dd dqb nc dqb nc adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss nc mode dqpb dqpa v ss bwb nc v dd nc bw a nc bwe v ss zz cy7c1382cv25 (1m x 18) cy7c1380cv25 (512k x 36) a a
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 5 of 33 pin configurations (continued) cy7c1380cv25 (512k x 36) - 11 x 15 fbga 165-ball bump fbga cy7c1382cv25 (1m x 18) - 11 x 15 fbga 234567 1 a b c d e f g h j k l m n p r tdo nc nc nc nc dpb nc dqb ace 1 nc ce 3 bw bbwe ace 2 nc dqb dqb mode nc dqb dqb nc nc nc 36m 72m v ddq nc bw aclk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss a v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss atdi atms dqb v ss nc v ss dqb nc v ss v ss v ss v ss v ss v ss v ss a1 dqb nc nc nc v ddq v ss 891011 a adv a adsc a oe adsp a 144m v ss v ddq nc dpa v ddq v dd nc dqa dqa nc nc nc dqa nc v dd v ddq v dd v ddq dqa v dd nc v dd nc v dd v ddq dqa v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss aa aa dqa nc nc zz dqa nc nc dqa a v ddq 234567 1 a b c d e f g h j k l m n p r tdo nc nc dpc dqc dpd nc dqd ace 1 bw bce 3 bw cbwe ace 2 dqc dqd dqd mode nc dqc dqc dqd dqd dqd 36m 72m v ddq bw dbw aclk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss a v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss atdi atms dqc v ss dqc v ss dqc dqc v ss v ss v ss v ss v ss v ss v ss a1 dqd dqd nc nc v ddq v ss 891011 a adv a adsc nc oe adsp a144m v ss v ddq nc dpb v ddq v dd dqb dqb dqb nc dqb nc dqa dqa v dd v ddq v dd v ddq dqb v dd nc v dd dqa v dd v ddq dqa v ddq v dd v dd v ddq v dd v ddq dqa v ddq a a v ss aa aa dqb dqb dqb zz dqa dqa dpa dqa a v ddq
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 6 of 33 pin definitions name i/o description a0 a1 a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a [1:0] feed the 2-bit counter. bwa bwb bwc bwd input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw a,b,c,d and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input-clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ig- nored if ce 1 is high. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. (tqfp only) ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. (tqfp only) oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk . when asserted, it automatically increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk . when asserted low, a is captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk . when asserted low, a [x:0] is captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. mode input-pin selects burst order . when tied to gnd selects linear burst sequence. when tied to v ddq or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. zz input- asynchronous zz ? sleep ? input . this active high input places the device in a non-time critical ? sleep ? condition with data integrity preserved. dqa, dpa dqb, dpb dqc, dpc dqd, dpd i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a [x] during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqx and dpx are placed in a three-state condition. dq a,b,c, and d are 8 bits wide and the dp a,b,c, and d are 1 bit wide. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. (bga only) tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck.(bga only)
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 7 of 33 tms tes t m o de s el e ct synchronous this pin controls the test access port state machine . sampled on the rising edge of tck. (bga only) tck jtag serial clock serial clock to the jtag circuit . (bga only) v dd power supply power supply inputs to the core of the device . should be connected to 2.5v 5% power supply. v ss ground ground for the core of the device . should be connected to ground of the system. v ddq i/o power supply power supply for the i/o circuitry . v ssq i/o ground ground for the i/o circuitry . should be connected to ground of the system. nc - no connects .pins are not internally connected. 36m 72m 144m - no connects . reserved for address expansion. pin definitions name i/o description
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 8 of 33 introduction functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. max- imum access delay from the clock rise (t co ) is 2.6 ns (250-mhz device). the cy7c1380cv25/cy7c1382cv25 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium ? and i486 processors. the linear burst sequence is suited for pro- cessors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode in- put. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw a,b,c,d for cy7c1380v25 and bw a,b for cy7c1382v25) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. synchronous chip selects (ce 1 , ce 2 , ce 3 for tqfp / ce 1 for bga) and an asynchronous output enable (oe ) provide for easy bank selection and output three-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are sat- isfied at clock rise: (1) adsp or adsc is asserted low, (2) chip selects are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs is stored into the address advancement logic and the address register while being presented to the memory core. the cor- responding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. after the first cycle of the access, the outputs are controlled by the oe signal. consecutive single read cycles are supported. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output will three-state immediately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) chip select is asserted active. the address presented is load- ed into the address register and the address advancement logic while being delivered to the ram core. the write signals (gw , bwe , and bw x) and adv inputs are ignored during this first cycle. adsp triggered write accesses require two clock cycles to complete. if gw is asserted low on the second clock rise, the data presented to the dqx inputs is written into the corre- sponding address location in the ram core. if gw is high, then the write operation is controlled by bwe and bw x sig- nals. the cy7c1380cv25/cy7c1382cv25 provides byte write capability that is described in the write cycle description table. asserting the byte write enable input (bwe ) with the selected byte write (bw a,b,c,d for cy7c1380cv25 and bw a,b for cy7c1382cv25) input will selectively write to only the desired bytes. bytes not selected during a byte write oper- ation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1380cv25/cy7c1382cv25 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq inputs. doing so will three- state the output drivers. as a safety precaution, dq are auto- matically three-stated whenever a write cycle is detected, re- gardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw x) are asserted active to conduct a write to the desired byte(s). adsc triggered write accesses require a single clock cycle to complete. the address presented to a [17:0] is loaded into the address register and the address advancement logic while being delivered to the ram core. the adv input is ig- nored during this cycle. if a global write is conducted, the data presented to the dq[x:0] is written into the corresponding ad- dress location in the ram core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1380cv25/cy7c1382cv25 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq[x:0] inputs. doing so will three-state the output drivers. as a safety precaution, dq[x:0] are automatically three-stated whenever a write cycle is de- tected, regardless of the state of oe . burst sequences the cy7c1380cv25/cy7c1382cv25 provides a two-bit wraparound counter, fed by a [1:0] , that implements either an interleaved or linear burst sequence. the interleaved burst se- quence is designed specifically to support intel ? pentium ap- plications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst se- quence is user selectable through the mode input. asserting adv low at clock rise will automatically increment the burst counter to the next address in the burst sequence. both read and write burst operations are supported.
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 9 of 33 sleep mode the zz input pin is an asynchronous input. asserting zz plac- es the sram in a power conservation ? sleep ? mode. two clock cycles are required to enter into or exit from this ? sleep ? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ? sleep ? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ? sleep ? mode. ce s, adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst sequence first address second address third address fourth address a [1:0]] a [1:0] a [1:0] a [1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst sequence first address second address third address fourth address a [1:0] a [1:0] a [1:0] a [1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode stand- by current zz > v dd ? 0.2v 60 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 10 of 33 cycle descriptions [1, 2, 3, 4] next cycle add. used zz ce 3 ce 2 ce 1 adsp adsc adv oe dq write unselected none 0 x x 1 x 0 x x hi-z x unselected none 0 1 x 0 0 x x x hi-z x unselected none 0 x 0 0 0 x x x hi-z x unselected none 0 1 x 0 1 0 x x hi-z x unselected none 0 x 0 0 1 0 x x hi-z x begin read external 0 0 1 0 0 x x x hi-z x begin read external 0 0 1 0 1 0 x x hi-z read continue read next 0 x x x 1 1 0 1 hi-z read continue read next 0 x x x 1 1 0 0 dq read continue read next 0 x x 1 x 1 0 1 hi-z read continue read next 0 x x 1 x 1 0 0 dq read suspend read current 0 x x x 1 1 1 1 hi-z read suspend read current 0 x x x 1 1 1 0 dq read suspend read current 0 x x 1 x 1 1 1 hi-z read suspend read current 0 x x 1 x 1 1 0 dq read begin write current 0 x x x 1 1 1 x hi-z write begin write current 0 x x 1 x 1 1 x hi-z write begin write external 0 0 1 0 1 0 x x hi-z write continue write next 0 x x x 1 1 0 x hi-z write continue write next 0 x x 1 x 1 0 x hi-z write suspend write current 0 x x x 1 1 1 x hi-z write suspend write current 0 x x 1 x 1 1 x hi-z write zz ? sleep ? none 1 x x x x x x x hi-z x notes: 1. x = ? don't care, ? 1 = high, 0 = low. 2. write is defined by bwe , bw x , and gw . see write cycle descriptions table. 3. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 4. ce 1 , ce 2 and ce 3 are available only in the tqfp package. the bga package has a single chip select, ce 1 .
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 11 of 33 notes: 5. the sram always initiates a read cycle when adsp asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to three-state. oe is a ? don't care ? for the remainder of the write cycle. 6. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dq = high-z when oe is inactive or when the device is deselected, and dq = data when oe is active. write cycle descriptions [1, 5, 6] function (1380cv25) gw bwe bw dbw cbw bbw a read 1 1xxxx read 101111 write byte 0 ? dqa 101110 write byte 1 ? dqb 101101 write bytes 1, 0 101100 write byte 2 ? dqc 101011 write bytes 2, 0 101010 write bytes 2, 1 101001 write bytes 2, 1, 0 1 0 1 0 0 0 write byte 3 ? dqd 100111 write bytes 3, 0 100110 write bytes 3, 1 100101 write bytes 3, 1, 0 1 0 0 1 0 0 write bytes 3, 2 100011 write bytes 3, 2, 0 1 0 0 0 1 0 write bytes 3, 2, 1 1 0 0 0 0 1 write all bytes 1 0 0 0 0 0 write all bytes 0 x x x x x function (1382cv25) gw bwe bw bbw a read 1 1 x x read 1 0 1 1 write byte 0 ? dq [7:0] and dp 0 1010 write byte 1 ? dq [15:8] and dp 1 1001 write all bytes 1 0 0 0 write all bytes 0 x x x
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 12 of 33 ieee 1149.1 serial boundary scan (jtag) the cy7c1380cv25/cy7c1382cv25 incorporates a serial boundary scan test access port (tap) in the bga package only. the tqfp package does not offer this functionality. this port operates in accordance with ieee standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 2.5v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are in- ternally pulled up and may be unconnected. they may alter- nately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the oper- ation of the device. test access port (tap) ? test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the regis- ters and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruc- tion that is loaded into the tap instruction register. for infor- mation on loading the instruction register, see the tap con- troller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the e output is active depending upon the current state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operat- ing. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuit- ry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as de- scribed in the previous section. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (vss) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 configuration has a 70-bit-long reg- ister, and the x18 configuration has a 51-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register defi- nitions table. tap instruction set eight different instructions are possible with the three-bit in- struction register. all combinations are listed in the instruction code table. three of these instructions are listed as re- served and should not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller can- not be used to load address, data or control signals into the
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 13 of 33 sram and cannot preload the input or output buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather it performs a capture of the inputs and output ring when these instructions are executed. instructions are loaded into the tap controller during the shift- ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be ex- ecuted whenever the instruction register is loaded with all 0s. extest is not implemented in the tap controller, and there- fore this device is not compliant to the 1149.1 standard. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. unlike the sample/preload instruction, ex- test places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or when- ever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is cap- tured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possi- ble that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller ? s capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update- dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction reg- ister and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advan- tage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 14 of 33 tap controller state diagram test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-dr shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 note: the 0/1 next to each state represents the value at tms at the rising edge of tck.
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 15 of 33 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . x 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical characteristics over the operating range [7, 8] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 1.0 ma 1.7 v v oh2 output high voltage i oh = ? 100 a 2.1 v v ol1 output low voltage i ol = 1.0 ma 0.4 v v ol2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 1.7 v dd + 0.3 v v il input low voltage ? 0.3 0.7 v i x input load current gnd < v i < v ddq ? 5 5 a notes: 7. all voltage referenced to ground. 8. overshoot: v ih (ac) < v dd +1.5v for t < t tcyc /2, undershoot: v il (ac) > ? 0.5v for t < t tcyc /2.
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 16 of 33 tap ac switching characteristics over the operating range [9, 10] parameters description min. max unit t tcyc tck clock cycle time 100 ns t tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns notes: 9. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 v/ns.
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 17 of 33 tap timing and test conditions (a) tdo c l = 20 pf z 0 = 50 ? gnd 1.25v 50 ? 2.5v 0v all input pulses 1.25v test clock test mode select tck tms test data-in tdi test data-out t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdov t tdox tdo
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 18 of 33 identification register definitions instruction field 512k x 36 1m x 18 description revision number (31:28) 0100 0100 reserved for version number cypress device id (27:24) 1011 1011 reserved for internal use device type (23:18) 000000 000000 defines memory type and architecture device width and density (17:12) 100101 010101 defines width and density cypress jedec id (11:0) 000001101001 000001101001 allows unique identification of sram vendor scan register sizes register name bit size (x18) bit size (x36) instruction 3 3 bypass 1 1 id 32 32 boundary scan 51 70 identification codes instruction code description extest 000 captures the input/output ring contents. places the boundary scan register between the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. idcode 001 loads the id register with the vendor id code and places the register be- tween tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/output contents. places the boundary scan register be- tween tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation.
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 19 of 33 boundary scan order (512k x 36) bit # signal name bump id bit # signal name bump id 1 tbd tbd 36 tbd tbd 2 tbd tbd 37 tbd tbd 3 tbd tbd 38 tbd tbd 4 tbd tbd 39 tbd tbd 5 tbd tbd 40 tbd tbd 6 tbd tbd 41 tbd tbd 7 tbd tbd 42 tbd tbd 8 tbd tbd 43 tbd tbd 9 tbd tbd 44 tbd tbd 10 tbd tbd 45 tbd tbd 11 tbd tbd 46 tbd tbd 12 tbd tbd 47 tbd tbd 13 tbd tbd 48 tbd tbd 14 tbd tbd 49 tbd tbd 15 tbd tbd 50 tbd tbd 16 tbd tbd 51 tbd tbd 17 tbd tbd 52 tbd tbd 18 tbd tbd 53 tbd tbd 19 tbd tbd 54 tbd tbd 20 tbd tbd 55 tbd tbd 21 tbd tbd 56 tbd tbd 22 tbd tbd 57 tbd tbd 23 tbd tbd 58 tbd tbd 24 tbd tbd 59 tbd tbd 25 tbd tbd 60 tbd tbd 26 tbd tbd 61 tbd tbd 27 tbd tbd 62 tbd tbd 28 tbd tbd 63 tbd tbd 29 tbd tbd 64 tbd tbd 30 tbd tbd 65 tbd tbd 31 tbd tbd 66 tbd tbd 32 tbd tbd 67 tbd tbd 33 tbd tbd 68 tbd tbd 34 tbd tbd 69 tbd tbd 35 tbd tbd 70 tbd tbd boundary scan order (1m x 18) bit # signal name bump id bit # signal name bump id 1 tbd tbd 36 tbd tbd 2 tbd tbd 37 tbd tbd 3 tbd tbd 38 tbd tbd 4 tbd tbd 39 tbd tbd 5 tbd tbd 40 tbd tbd 6 tbd tbd 41 tbd tbd 7 tbd tbd 42 tbd tbd 8 tbd tbd 43 tbd tbd 9 tbd tbd 44 tbd tbd 10 tbd tbd 45 tbd tbd 11 tbd tbd 46 tbd tbd 12 tbd tbd 47 tbd tbd 13 tbd tbd 48 tbd tbd 14 tbd tbd 49 tbd tbd 15 tbd tbd 50 tbd tbd 16 tbd tbd 51 tbd tbd 17 tbd tbd 52 tbd tbd 18 tbd tbd 53 tbd tbd 19 tbd tbd 54 tbd tbd 20 tbd tbd 55 tbd tbd 21 tbd tbd 56 tbd tbd 22 tbd tbd 57 tbd tbd 23 tbd tbd 58 tbd tbd 24 tbd tbd 59 tbd tbd 25 tbd tbd 60 tbd tbd 26 tbd tbd 61 tbd tbd 27 tbd tbd 62 tbd tbd 28 tbd tbd 63 tbd tbd 29 tbd tbd 64 tbd tbd 30 tbd tbd 65 tbd tbd 31 tbd tbd 66 tbd tbd 32 tbd tbd 67 tbd tbd 33 tbd tbd 68 tbd tbd 34 tbd tbd 69 tbd tbd 35 tbd tbd 70 tbd tbd
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 20 of 33 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 55 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage on v dd relative to gnd ....... ? 0.3v to +3.6v dc voltage applied to outputs in high z state [11] ................................ ? 0.5v to v ddq + 0.5v dc input voltage [11] ............................ ? 0.5v to v ddq + 0.5v current into outputs (low) .........................................20 ma static discharge voltage........................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma notes: 11. minimum voltage equals ? 2.0v for pulse durations of less than 20 ns. 12. t a is the temperature. operating range range ambient temp. [12] v dd/ v ddq com ? l 0 c to 70 c 2.5v 5% ind ? l ? 40 c to +85 c electrical characteristics over the operating range parameter description test conditions min. max. unit v dd /v ddq power supply voltage 2.375 2.625 v v oh output high voltage v dd = min., i oh = ? 1.0 ma 2.0 v v ol output low voltage v dd = min., i ol = 1.0 ma 0.4 v ih input high voltage 1.7 v dd + 0.3 v il input low voltage [11] ? 0.3 0.7 i x input load current except zz and mode gnd < v i < v ddq ? 5 5 a i zz input current of mode ? 30 30 a input current of zz input = v ss ? 30 30 a i oz output leakage current gnd < v i < v ddq, output disabled ? 5 5 a i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 350 ma 4.4-ns cycle, 225 mhz 325 ma 5.0-ns cycle, 200 mhz 300 ma 6.0-ns cycle, 167 mhz 275 ma i sb1 automatic ce power- down current ? ttl inputs max. v dd , device deselected, v in > v ih or v in < v il f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 120 ma 4.4-ns cycle, 225 mhz 110 ma 5.0-ns cycle, 200 mhz 100 ma 6.0-ns cycle, 167 mhz 90 ma i sb2 automatic ce power- down current ? cmos inputs max. v dd , device deselected, v in < 0.3v or v in > v ddq ? 0.3v, f = 0 all speed grades 70 ma i sb3 automatic ce power- down current ? cmos inputs max. v dd , device deselected, or v in < 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 105 ma 4.4-ns cycle, 225 mhz 100 ma 5.0-ns cycle, 200 mhz 95 ma 6.0-ns cycle, 167 mhz 85 ma i sb4 automatic ce power- down current ? ttl inputs max. v dd , device deselected, v in > v ih or v in < v il , f = 0 all speeds 80 ma shaded areas contain advance information.
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 21 of 33 capacitance [13] parameter description test conditions max. unit 100-tqfp 119-bga 165-fbga c in input capacitance t a = 25 c, f = 1 mhz tbd tbd tbd pf c clk clock input capacitance tbd tbd tbd pf c i/o input/output capacitance tbd tbd tbd pf ac test loads and waveforms [14] output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) v ddq all input pulses [10] 2.5v gnd 90% 10% 90% 10% 1 ns 1 ns (c) output r t = 50 ? z 0 = 50 ? v t = 1.25 30 pf v t - termination voltage r t - termination resistance thermal resistance [13] description test conditions symbol tqfp 119 bga 165 fbga unit thermal resistance (junction to ambient) still air, soldered on a 3 x 4.5 inch 2 , 2-layer printed circuit board ja 31 45 46 c/w thermal resistance (junction to case) jc 673 c/w notes: 13. tested initially and after any design or process changes that may affect these parameters. 14. input waveform should have a slew rate of < 1 ns.
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 22 of 33 switching characteristics over the operating range [15, 16, 17] -250 -225 -200 -167 parameter description min. max. min. max. min. max. min. max. unit t cyc clock cycle time 4.0 4.4 5 6 ns t ch clock high 1.7 2.0 2.0 2.2 ns t cl clock low 1.7 2.0 2.0 2.2 ns t as address set-up before clk rise 1.2 1.4 1.4 1.5 ns t ah address hold after clk rise 0.3 0.4 0.4 0.5 ns t co data output valid after clk rise 2.6 2.8 3.0 3.4 ns t doh data output hold after clk rise 1.0 1.0 1.3 1.3 ns t ads adsp , adsc set-up before clk rise 1.2 1.4 1.4 1.5 ns t adh adsp , adsc hold after clk rise 0.3 0.4 0.4 0.5 ns t wes bwe , gw , bw x set-up before clk rise 1.2 1.4 1.4 1.5 ns t weh bwe , gw , bw x hold after clk rise 0.3 0.4 0.4 0.5 ns t advs adv set-up before clk rise 1.2 1.4 1.4 1.5 ns t advh adv hold after clk rise 0.3 0.4 0.4 0.5 ns t ds data input set-up before clk rise 1.2 1.4 1.4 1.5 ns t dh data input hold after clk rise 0.3 0.4 0.4 0.5 ns t ces chip enable set-up 1.2 1.4 1.4 1.5 ns t ceh chip enable hold after clk rise 0.3 0.4 0.4 0.5 ns t chz clock to high-z [16] 2.6 2.8 3.0 3.4 ns t clz clock to low-z [16] 1.0 1.0 1.3 1.3 ns t eohz oe high to output high-z [16, 17] 2.6 2.8 3.0 3.4 ns t eolz oe low to output low-z [16, 17] 0 0 0 0 ns t eov oe low to output valid [16] 2.6 2.8 3.0 3.4 ns shaded areas contain preliminary information. notes: 15. unless otherwise noted, test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.25v, inp ut pulse levels of 0 to 2.5v, and output loading of the specified i ol /i oh and load capacitance. shown in (a), (b) and (c) of ac test loads. 16. t chz , t clz , t oev , t eolz , and t eohz are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 200 mv from steady- state voltage. 17. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz .
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 23 of 33 1 switching waveforms write cycle timing [4, 18, 19, 20] notes: 18. we is the combination of bwe and bw x to define a write cycle (see write cycle descriptions table). 19. wdx stands for write data to address x. 20. device originally deselected. adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 1a data in t cyc t ch t cl t ads t adh t ads t adh t advs t advh wd1 wd2 wd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh 2b 3a 1a single write burst write unselected adsp ignored with ce 1 inactive ce 1 masks adsp = don ? t care = undefined pipelined write 2a 2c 2d t dh t ds high-z high-z unselected with ce 2 adv must be inactive for adsp write adsc initiated write
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 24 of 33 read cycle timing [4, 18, 20, 21] note: 21. rdx stands for read data from address x. switching waveforms (continued) adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 2a 2c 1a data out t cyc t ch t cl t ads t adh t ads t adh t advs t advh rd1 rd2 rd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh t co t eov 2b 2c 2d 3a 1a t oehz t doh t clz t chz single read burst read unselected adsp ignored with ce 1 inactive suspend burst ce 1 masks adsp = don ? t care = undefined pipelined read adsc initiated read unselected with ce 2
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 25 of 33 read/write cycle timing [4, 18, 19, 20, 21] switching waveforms (continued) adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 1a data in/out t cyc t ch t cl t ads t adh t advs t advh rd1 wd2 wd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh t eolz t co t eov 4a 4c 4d 1a t eohz t doh t chz single read burst read = don ? t care = undefined pipelined read out 2a in 4b out out out out single write t ds t dh single write rd4 rd5 single cycle deselect i/o disabled within one clock cycle after deselect 3a in ce 1 unselected
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 26 of 33 pipelined read/write timing [4, 18, 19, 20, 21] switching waveforms (continued) adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 1a data in/out rd1 rd2 5a 7a 1a = don ? t care = undefined out 2a out 6a in in in adsp read adsc write adsc read rd3 rd4 3a out 4a out adsp write unselected wd5 wd6 wd7 wd8 selected
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 27 of 33 switching waveforms (continued) oe three-state i/os t eohz t eov t eolz oe switching waveforms
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 28 of 33 notes: 22. device must be deselected when entering zz mode. see cycle descriptions table for all possible signal conditions to deselect the device. 23. i/os are in three-state when exiting zz sleep mode. switching waveforms (continued) adsp clk adsc ce 1 ce 3 low high zz t zzs t zzrec i dd i dd (active) three-state i/os zz mode timing [4, 22, 23] ce 2 i ddzz high
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 29 of 33 ordering information speed (mhz) ordering code package name package type operating range 250 cy7c1382cv25-250ac cy7c1380cv25-250ac a101 100-lead thin quad flat pack commercial cy7c1382cv25-250bgc cy7c1380cv25-250bgc bg119 119 pbga cy7c1382cv25-250bzc cy7c1380cv25-250bzc bb165a 165 fbga 225 cy7c1382cv25-225ac cy7c1380cv25-225ac a101 100-lead thin quad flat pack cy7c1382cv25-225bgc cy7c1380cv25-225bgc bg119 119 pbga cy7c1382cv25-225bzc cy7c1380cv25-225bzc bb165a 165 fbga 200 cy7c1382cv25-200ac cy7c1380cv25-200ac a101 100-lead thin quad flat pack cy7c1382cv25-200bgc cy7c1380cv25-200bgc bg119 119 pbga cy7c1382cv25-200bzc cy7c1380cv25-200bzc bb165a 165 fbga 167 cy7c1382cv25-167ac cy7c1380cv25-167ac a101 100-lead thin quad flat pack cy7c1382cv25-167bgc cy7c1380cv25-167bgc bg119 119 pbga cy7c1382cv25-167bzc cy7c1380cv25-167bzc bb165a 165 fbga 225 cy7c1382cv25-225ai cy7c1380cv25-225ai a101 100-lead thin quad flat pack industrial cy7c1382cv25-225bgi cy7c1380cv25-225bgi bg119 119 pbga cy7c1382cv25-225bzi cy7c1380cv25-225bzc bb165a 165 fbga 200 cy7c1382cv25-200ai cy7c1380cv25-200ai a101 100-lead thin quad flat pack cy7c1382cv25-200bgi cy7c1380cv25-200bgi bg119 119 pbga cy7c1382cv25-200bzi cy7c1380cv25-200bzi bb165a 165 fbga 167 CY7C1382CV25-167AI cy7c1380cv25-167ai a101 100-lead thin quad flat pack cy7c1382cv25-167bgi cy7c1380cv25-167bgi bg119 119 pbga cy7c1382cv25-167bzi cy7c1380cv25-167bzi bb165a 165 fbga shaded areas contain advance information and parts that may not be offered.
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 30 of 33 package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 31 of 33 package diagrams (continued) 165-ball fbga (13 x 15 x 1.2 mm) bb165a 51-85122-*c
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 32 of 33 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. intel and pentium are registered trademarks of intel corporation. all product and company names mentioned in this document may be trademarks of their respective holders. package diagrams (continued) 51-85115-*b 119-lead pbga (14 x 22 x 2.4 mm) bg119
cy7c1380cv25 cy7c1382cv25 preliminary document #: 38-05240 rev. *a page 33 of 33 document history page document title: cy7c1380cv25/cy7c1382cv25 512k x 36/1m x 18 pipelined sram document number: 38-05240 rev. ecn no. issue date orig. of change description of change ** 116280 08/29/02 skx new data sheet *a 121543 11/21/02 dsg updated package diagrams 51-85115 (bg119) to rev. *b and 51-85122 (bb165a) to rev. *c

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